Intel, Numonyx hail phase change memory breakthrough

Robert Hallock (Thrax) Intel and Numonyx have made an important discovery in Phase Change Memory, the technology that may one day replace NAND and DRAM.

October 28, 2009 10:24 PM ET in Articles, , , , , , ,

Numonyx_VD_RGB-545_270x226Intel and Numonyx are today announcing a key breakthrough in the development of Phase Change Memory (PCM) technology.

The breakthrough has enabled the partnership to develop a 64Mb test chip that demonstrates multiple layers of PCM arrays on a single die. These findings will enable future PCM-based devices to offer lower power consumption, higher capacity and greater storage density.

The company is calling the breakthrough chip a PCMS, or Phase Change Memory and Switch. The PCMS interleaves layers of thin-film PCM arrays with controlling thin-film selectors called Ovonic Transfer Switches (OTS). The sandwiched PCM and OTS layers are arranged in a crosspoint architecture and fitted to a CMOS substrate to create high-density, high-bandwidth PCM cells.

What is phase change memory?

Phase change memory is an interesting technology that relies on the the curious properties of chalcogenide glass, which changes phases of matter with the application of voltage.

Early attempts at PCM development defined two states of matter: The first being an amorphous solid, the second a hard crystalline structure. In the case of the former, the high resistance of the amorphous state indicates a binary zero, and the low-resistance crystalline state represents a binary one. More recent developments have discovered two additional states, bringing the storage density up to four states, or in line with the density primarily offered by MLC NAND cells.

Why phase change memory?

PCM’s characteristics make it something of a Holy Grail amongst memory researchers. For starters, the current crop of NAND-based storage devices represent their data by trapping electrons. Scientists believe that it will not be possible to store electrons in NAND cells manufactured on a process node any smaller than 20nm. PCM, however, is seen as a viable technology down to the 5nm level.

PCM also ends the write endurance debate which continues to shroud NAND technology in a shadow of doubt. Because PCM uses the electrical resistance of matter states to represent binary data, it offers an unlimited number of write cycles.

“This is important as traditional flash memory technologies face certain physical limits and reliability issues, yet demand for memory continues to rise in everything from mobile phones to data centers,” said Greg Atwood, Senior Technology Fellow at Numonyx.

This differs from NAND which uses charges of up to 20V to read, write or erase data; these charges ultimately destroy a NAND cell’s ability to read or write new information.

Phase change may even unify mass and volatile storage technologies by replacing DRAM as well. Al Fazio, Intel Fellow and Director of Memory Technology Development, explains.

“You have a memory technology that looks like memory–in other words, hardware can do a load/store because it can act on a small chunk of data with a low latency, yet it’s non-volatile so that it has the non-volatile aspects of storage.”

With a write latency of 1µs, PCM is 20x faster than DRAM.

With a write latency of 1µs, PCM is 20x faster than DRAM.

This means that memory modules based on PCM could operate at the speed of DRAM, but retain their data even through power loss.  Imagine how quickly a PC might boot if the operating system’s last environment state was ready to go in memory the moment the PC was powered on.

Because PCM cells are byte-addressable, rather than grouped into 512KB blocks as with NAND, PCM-based storage solutions would offer the consistent read/write performance we see in today’s desktop memory. No more optimal write sizes, no more write amplification, and no more trading between IOPS and throughput.

Looking ahead

Phase change memory is very much an infant product. Vendors like Intel, Samsung, and Numonyx are working feverishly to further improve capacity and speed before the technology can go into production. We must also consider their efforts in the context of PCM’s glacial development, which thus far spans over forty years. It can easily be surmised, then, that a foundry configured to produce PCM cells falls on the far side of five years out.

Even so, the significance of the Intel/Numonyx PCMS should not be underestimated. A stackable, high-density, high-throughput PCM chip is an outstanding achievement in the ongoing efforts to realize a commercial product.

In the mean time, Fazio and Atwood are preparing their research for the International Electron Devices Meeting (IEDM) in December where it will be presented by Intel Senior Principal Engineer DerChang Kau.

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17 Comments:

  1. PCM also ends the write endurance debate which continues to shroud NAND technology in a shadow of doubt. Because PCM uses the electrical resistance of matter states to represent binary data, it offers an unlimited number of write cycles.

    What makes them think that the voltage application to change phases won't eventually wreck the phase changing mechanism, leading to the same cell degradation issues that affect NAND? Seems like the same kind of issues to me - or have I missed something?

    Imagine how quickly a PC might boot if the operating system’s last environment state was ready to go in memory the moment the PC was powered on.

    Imagine the security implications of such a scenario, too.

    Neat tech; been watching this for a while, but nice to see a breakthrough.

  2. Technically speaking, yes, it will eventually wreck the cells, but the earliest sample cells boasted 100,000,000 write cycles, or a 100x increase in even the most robust NAND cells with 20 years of R&D. Practically speaking, PRAM is no more limited than writing to a regular hard drive.

    EDIT FOR CLARITY: 1,000,000 cycles is an SLC NAND endurance figure. Since PMC can store two bits per cell, it's similar to MLC NAND. Based on that metric, PMC is ~2857x more reliable.

  3. Imagine the security implications of such a scenario, too.

    At the OS level, they're no more than current suspend/hibernate scenarios. Requiring authentication on resume is pretty standard practice these days, at least in the business world (which is where any security concerns would be based to begin with).

    As for the removing memory to read while the machine is offline, that's definitely something that will need to be addressed, and I'm sure it would be before they thought of pushing this technology out as a DRAM solution.

    Outside of that, a 5nm process would allow for some phenomenal cell density. Once I can have my 2TB flash drive in my pocket, I'll be a very happy man.

  4. The security risk of a non-volatile PRAM module is no different than the risk profile presented by a hard drive. Both require physical access and if that is your security breach, you already have bigger concerns than data theft.

  5. The security risk of a non-volatile PRAM module is no different than the risk profile presented by a hard drive. Both require physical access and if that is your security breach, you already have bigger concerns than data theft.

    Of course, this won't stop the same twonks that ran around like their hair was on fire when they discovered that under the correct (arguably super-extreme) conditions, you could read the RAM of a shut-down workstation/laptop.

  6. Not entirely true, Rob. There have been proof-of-concept attacks where, for example, you freeze the RAM's ICs before they have a chance to lose their data. Doing so can get an enterprising hacker a RAM dump and get them an encryption key or various other gems hidden in memory. This removes the need for urgency - if the data stays there without freezing or various other extreme interventions, that data's there for anybody to dump.

    I'm not saying that you could be safe even in the event of physical breaches, but it does make it theoretically easier.

  7. Not entirely true, Rob. There have been proof-of-concept attacks where, for example, you freeze the RAM's ICs before they have a chance to lose their data. Doing so can get an enterprising hacker a RAM dump and get them an encryption key or various other gems hidden in memory. This removes the need for urgency - if the data stays there without freezing or various other extreme interventions, that data's there for anybody to dump.

    I'm not saying that you could be safe even in the event of physical breaches, but it does make it theoretically easier.

    His statement still holds true, though. If you've suffered a physical security breach (someone else has their hands on your hardware), you have other issues to deal with.

  8. Of course, this won't stop the same twonks that ran around like their hair was on fire when they discovered that under the correct (arguably super-extreme) conditions, you could read the RAM of a shut-down workstation/laptop.
  9. And my "not entirely true" references your mention that possessing the hard drive is the same end result of possessing non-volatile RAM and the hard disk. A disk alone, if encrypted well enough, could be safe. There are also ways around that, yes. But having a key stuck in memory just makes it easier and less destructive.

    And again, my point was that this RAM erases the need for "arguably super-extreme" conditions to achieve the same result. That's all...

  10. Storing a plaintext key in memory is just as silly.

  11. Byte-vs-block addressing is a function of how the storage device is built, not a limitation of the technology. Essentially all embedded devices using Flash MTDs use byte addressing. SSDs use block addressing because it allows them to be used with existing standard interfaces and filesystems.

    This technology looks remarkably similar to phase-change shape memory alloys. When heated they switch from one crystalline configuration to another and switch back when cooled. The ones I've played with have latencies measurable in seconds but then again they weren't 40nm wide either.

    Also, we've got to come up with a new acronym for this technology. PCM already has a definition in the context of computers and electronics. (pulse-coded modulation.)

    -drasnor

  12. The alternative acronym that's bandied about is PRAM. I don't have a preference for either.

    @Dras: PCM switches states in about 1µs. That's about 20x faster than DRAM's write latency.

  13. Thrax, do you have a source for that? I'm seeing this:

    By heating the chalcogenide to a temperature above its crystallization point, but below the melting point, it will transform into a crystalline state with a much lower resistance. The time to complete this phase transition is temperature-dependent. Cooler portions of the chalcogenide take longer to crystallize, and overheated portions may be remelted. Commonly, a crystallization time scale on the order of 100 ns is used. This is longer than conventional volatile memory devices like modern DRAM, which have a switching time on the order of two nanoseconds. However, a January 2006 Samsung Electronics patent application indicates PRAM may achieve switching times as fast as five nanoseconds.

    via

  14. Outdated information is outdated. GG Wikipedia.

    Here's Numonyx's PCM whitepaper (PDF).

    I've attached the relevant image.

  15. The alternative acronym that's bandied about is PRAM. I don't have a preference for either.

    @Dras: PCM switches states in about 1µs. That's about 20x faster than DRAM's write latency.

    20x slower you mean, by the chart you just posted.

    -drasnor

  16. Indeed. Thrax, a microsecond is 1000 nanoseconds. Wikipedia has exactly the same information. It's still slower than today's DRAM.

  17. You got me on the latency bit. I definitely mixed micro and nano-, however in terms of raw throughput, PRAM is faster than NAND and comparable to DRAM.

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