Intel Corporation has recently announced that it has completed the research and development on the techniques that will be necessary to produce 32nm chips by 4Q09.

Though full details will not be available until next week’s International Electron Devices meeting, Intel cites a second-gen high-k process, 193nm immersion lithography patterning, and enhanced transistor straining as the leading contributers to the final technique.

Intel’s first generation hafnium-based high-k process has received accolades for being a primary building block of the Penryn architecture found in the Core 2 Duo 8000 and Core 2 Quad 9000 series. This high-k process replaced the long-standing silicon dioxide gates which are unable to resist quantum tunneling when shrinking architecture below the 65nm process used in the original Core 2 Duos.

Meanwhile, Intel’s 193nm immersion lithography technology has been in service since the 90nm era to print integrated circuits on wafers by beaming photons through a liquid medium. While alternatives have been under development for quite a while, none of them have been commercially viable. Due to recent refinements to this once unimagineable technique, it is expected that Intel will take it through to an 11nm process by 2015.

Lastly, the widely-used transistor straining process stretches the atomic structure of existing silicon atoms by aligning them with a silicon-germanium substrate. The SiGe crystalline structure is slightly wider than that of silicon’s, so the silicon’s atomic structure must artificially expand to adhere with the substrate. This process allows transistors to switch states at a much faster rate which allows everyone to enjoy faster IC performance.

It is expected that these and a myriad of other developments to be announced at the IEDM will be employed in the 32nm shrink of the Nehalem known as Sandy Bridge. Sandy Bridge chips are expected in 4Q09, and will fulfill Intel’s fourth year in adhering to their awarded tick-tock processor schedule.

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